Ternarylogic LLC offers a portfolio of inventions and technology that is based on MVL switching or n-state logic with n > 2. In the course of creating the n-state solutions it was demonstrated that some of the inventions can be used in binary switching.
Following are some elements of Ternarylogicís IP portfolio specifically targeted towards binary applications.
1. Correlation amplification
2. Binary latches not using NANDs or NORs
A patent on this invention has been issued as patent 7,365,576. The invention is based on a causal switching model that allows to model logic functions with feedback. It is shown that a combination of an AND and an OR function creates a memory latch. Two identical non-commutative functions, which represent the non-commutative expression a > b, allow for the creation of a very simple and inverterless binary latch.
3. Self-synchronizing LFSR descramblers in
A known disadvantage of the self-synchronizing LFSR scrambler and descrambler in Fibonacci configuration is that an LFSR with more than 2 taps require execution of additional XOR functions within a clock cycle. However, Fibonacci configured descramblers are preferred because of their self-synchronizing properties. Such a descrambler will flush errors and regain synchronization after the flushing of the shift register. To counter the disadvantage of multiple functions one generally applies LFSRs with just two taps, which are not always optimal.
Patent application 20070239812 discloses self-synchronizing scramblers and descramblers with LFSRs in Galois configuration. These LFSRs have more than 2 taps and functions and provide a greater variety of scrambling, while still being executed in one clock cycle and being self-synchronizing.
4. LFSR based pn-sequence detector
Detection of binary sequences is commonly performed by correlation techniques. This means that a sequence is compared bit-by-bit with a known sequence. Usually this requires that one locally generates the sequence that needs to be detected.
A pseudo-noise sequence is often generated by a self-running
LFSR. The pn-sequence is determined by the initial content of the shift
register. The pn-generator is from one perspective not provided with
an input. Patent application 20050184888
discloses how one can create an LFSR based descrambler for detection
of an LFSR based generated pn-sequence. Detection of the pn-sequence
generates a constant stream of 1s (or 0s if one so prefers).
6. Orthogonal hopping
7. Convolutional error correcting decoding
8. Binary scrambling of n-state symbols